Topics in hArdware SEcurity and RISC-V (TASER)

Leuven, September 18th, 2022

RISC-V logo


The open nature of, and both eco-system and community associated with RISC-V has arguably led to a "golden period" of research and innovation within the field of computer architecture. This, in turn, has positively impacted the associated field of hardware security, where significant existing challenges remain and new challenges continue to emerge. For example, use of RISC-V in this context offers opportunities (for academic and industrial research and development) which stem from the extensible, configurable nature of the ISA and many associated implementations, plus transparency afforded by access to HDL for many such implementations. Established in 2021 as a CHES affiliated event, the TASER workshop aims to 1) establish and solidify RISC-V as a topic of interest for CHES, and 2) act as an interface between the RISC-V and CHES communities.


Again operating as a CHES affiliated event, and held in-person, the half-day workshop will include a mixture of invited and submitted presentations. Per the associated CFP, we are inviting submission of presentation proposals: submit your proposal via the submission site before the deadline of 11/06/22 23:59:59 Anywhere on Earth (AoE).


The TASER 2022 workshop is affiliated with CHES 2022: please register with the conference to attend the workshop.